Meeting Minutes 2022-05-25

Voting Members :

  • antmicro
  • google
  • ibm
  • oregonstateuniversity
  • vantosh
Total voting members : 5 - Quorum voting members : 3

Attendees :

  • toddrosedahl - ibm
  • toshaanbharvani - vantosh
  • antonblanchard - ibm
  • michaelneuling - ibm
  • munirahmad - lattice
Voting member present : 2
This meeting does not have a voting member quorum.

LibreBMC SIG Meeting

Meeting date: 25 May 2022
Access link: https://zoom.us/j/91597478078
Meeting ID: 91597478078

Call to Order

Anti-trust Reminder

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Meeting Recording

Meeting is being recorded

AGENDA

Introduction

New folks this week?

New News

Any update?

Hardware Update

Bringup

  • AntMicro has all the HW it needs to do bring-up on the AC922.
    • However, they have very little time to spend on this
  • AntMicro will send a DC-SCM card to Toshaan
  • Todd will send an Interposer to Toshaan

OCP DC-SCM 2.0 Working Group – Meets bi-weekly

  • Final comments due 05/31
  • Todd to run a call with Google and some other key players to discuss our common direction for the 3.0 standard. WIP.

Conferences

  • Still working to set up various follow-ups
  • Goal is to have the bringup done with the DC-SCM/AC922 and showcase it at OCP22 10/18 and SC22 11/14
    • Could have 2 FPGAs
    • 1 is the BMC
    • The other FPGA could be some sort of a representation of the system
      • Implement HB on it?
      • Run QEMU?
      • Some other simulation running?

Communication / Collaboration

  • Calendar invites are working now it seems.

    • Cal invites did not work. Todd/Toshaan to work offline on it.
  • Standing Reminder: Everyone should be posting things into the #librebmc-sig slack channel.

Gateware

Update?

Simulation

  • Renode looks like a good option for a simulation environment for LibreBMC.
    • Todd to send note to Piotr with information on what we would like to do with Renode and where the links are to the code/etc. WIP

Soft Cores

  • OPF is funding an FPGA optimized POWER soft core
    • Target was “VexRISCV” resource usage and performance. **Todd to schedule a readout at a future meeting. Toshaan to check on when they could present

Toolchain

Updates?

Software

Updates?

FPGA Usage Barriers

  • List of opens (potential barriers) for using FPGAs as BMCs Update here?
    • Cost –
      • Projection is that will be cost competitive
      • Some things require an external chip
        • video driver, but could be added later
    • Soft Error Rates – Munir to follow up
      • Hard fails roughly the same as an ASIC
      • Looks like Xilinx SER FIT is reasonable (<200).
      • And detectable and fixable with an image reload
      • Lattice to provide data on FIT rates and recovery design
        • Munir to send an email with info
    • Performance? 8X slower than an ASPEED?
      • Information from Lattice
        • much faster to BMC to boot. 2min for ASPEED. 5sec for FGPA
          • This is mostly a function of the BMC stack, the ASPEED vs FPGA, so potentially not Apples to Apples (ASPEED vs FPGA)
        • Lattice to provide some information on this performance comparisons to ASPEED
        • How long will it take the system to boot on the FPGA?
        • Opening up of LTPI is under consideration (MIT)
    • Image size

Project Ideas – Running list of areas where we could use help

Workgroup Collaboration Tools

Community Involvement

  • Options for not needing an AC922

    • FPGA on both sides (emulating the HPM)
      • Raptor has such a board that has an FPGA on both sides
    • Can just use QEMU and simulate the AC922 side
  • How do we generate more activity/interest

    • Engage Universities – There are interested universities

    • Todd to start a list of universities and contacts New direction here. Todd/Toshaan to make an OPF page “Education Page” that points to these projects as well as the OpenPOWER curriculum being developed. Then we can all point our education contacts to that page. No need to list them here

    • Need clear work breakdown. We have this for some projects.

    • Need Mentors. True for Interns/MLH/etc, but many projects can be supported in the open

    • Offer badges/certificates

    • Offer Bounties

    • Major League Hacking Interships

      • Start end of May.
      • Need to sign up by end of March
      • Must have sponsors to guide students and hold office hours
      • We missed this window, but the next one starts in Sept and we will circle back on this in a month or so. We still need to think about detailed work tasks and who can be mentors
      • To use MLH, We need BoD (Board of Directors) approval
  • Need work items clearly identified and easily understood

    • Documentation – We need build instructions, readmes, etc

      • Need someone replicate the FPGA/OpenBMC load from scratch
        • Then document the process for others to follow so they can replicate the results
          • Build all pieces – Core, peripherals, OpenBMC,etc
        • Toshaan to take a crack at this now
    • Need official OpenBMC project and a makefile, bitbake/etc

    • Need the project broken down into manageable pieces

  • It was suggested that we should have a logo for libreBMC. Any thoughts from the team. Nice to have, but should not be a focus right now.

    • I did see an offer of help for a logo. I will follow up later. TBD

Goals – Need timelines on these – WIP

  • Tasks defined and project broken down
  • Able to generate a bitstream for an FPGA using fully open source toolchain.
  • Have RTL suitable for real production usage that has software support in the upstream OpenBMC project.
  • Someone seriously starting to do a real (non-development) LibreBMC deployment.
  • Fully functional Gateware and OpenBMC code stack for AC922
  • Determine the performance/size

Next Meeting

2022-06-30
30th of June 2022  @  22:00 UTC

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